FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters

Field programmable gate arrays (FPGAs) have been widely used in various application areas, such as industrial control, telecommunications and signal processing. To meet the diverse demands, each generation of commercial FPGAs comes with the architectural enhancements and a number of options covering specific application domains. The optimized architectures are usually generated from a time-consuming exploration with the existing CAD tools which map benchmark circuits on the alternative architectures under consideration. The analytical models, which use a series of equations to formulate metrics such as delay, area and power of FPGAs, were used to speed up the architectural exploration process. This paper aims at building an FPGA delay model considering both logic-level parameters and transistor-level parameters. This paper targets the classical island-style homogeneous FPGA architecture. An FPGA tile needs to be instantiated thousands of times for creating a complete FPGA. Therefore, the architecture exploration process is mainly performed for one tile. The delay of circuits which are mapped onto FPGA is related to the critical path in the FPGA tile. However, at the architecture design stage, the critical path is not known. To deal with this issue, we use the delay of the representative critical path containing all the unique subcircuits of the FPGA tile as the metric. We build the model based on the macro delay model and the RC model. In our work, after analyzing the equivalent RC models, the delay of each subcircuit in the FPGA representative critical path is formulated in the macro model. Then, the delays of the subcircuits are combined to produce an analytical delay model. In order to evaluate the proposed model, HSPICE is used to obtain the values of the critical path delay. The experimental results show that the proposed FPGA delay model achieves accuracy 11.5%, and two orders of magnitude speedup, compared to the HSPICE simulator.