A design guide of thermal resistance down to 30% for 3D multi-stack devices

This paper presents a design guide for reducing the thermal resistance of high-performance three-dimensional (3D) stacked integrated circuits (ICs) by comparing ICs with solder bump and bumpless interconnection structures. In this analysis, the total thermal resistance was estimated using the finite element method and thermal resistance network calculations. For conventional 3D stacked ICs with through-silicon vias (TSVs) and bumps, the interconnection layers, including dielectrics and organic layers, were the primary cause of thermal resistance. The thermal performance of a bumpless TSV IC stack was almost 150 times better than that of a conventional IC with the same TSV density. The total thermal resistance for organic layer thicknesses of 20 and 5μm was 1.54 and 0.46 Kcm
²
/W, respectively.