Nonlinear Jitter of a Clock Path Due to Electromagnetic Interference on the Supply

The paper presents a simple time-domain model for the nonlinear behavior of the jitter of a clock path due to electromagnetic interference on the power supply. A programming algorithm based on the model is developed to calculate the numerical value of the jitter. Transistor-level simulations and test-board measurements are performed on clock paths of various lengths to verify the jitter model. Good agreement between the experiments and MATLAB calculations are observed over wide ranges of interference frequencies and amplitudes. Interesting phenomena, such as the jitter-minimum shift and jitter inflection, can be explained and precisely predicted using the jitter model. An analytical equation is derived for the relationship between the interference frequency and amplitude for the jitter-minimum. The model requires only simple information from the gate circuit for the jitter calculation. It can be further developed into an analytical tool for predicting clock jitter under external electromagnetic interference.