Application debug in FPGAs in the presence of multiple asynchronous clocks

FPGAs have evolved rapidly over the past decade with a significant increase in size and complexity. Today's FPGA is indeed a system-on-chip (SOC) with a wide variety of hardened functionality, multiple asynchronous clock domains and widening interactions among different parts of the chip. It is commonplace to find applications that transfer data and control across clock-domains. This growing complexity, coupled with shrinking design cycles, has turned debug and verification into a critical design concern. Although software analysis tools have made significant progress over the years, this is not the case for debugging applications running on FPGAs. This paper describes a framework that enables non-intrusive application hardware debugging in the presence of multiple asynchronous clock domains. It offers full observability at minimal area and performance cost. The proposed approach uses Readback to retrieve the entire state of the circuit, a feature available in one form or another, in most commercial FPGAs today. Features such as single stepping and waveform reconstruction offer the same level of debug capability for applications accelerated on FPGAs, as simulation tools do for RTL implementations.