FPGA-based acceleration of FDAS module using OpenCL

The Square Kilometre Array (SKA) project will be the world largest radio telescope array. With the growth of the number of antennas, the signals that need to be processed increase dramatically. One import element of the SKA central signal processor (CSP) package is pulsar search. This paper focuses on the FPGA-based acceleration of the frequency-domain acceleration search (FDAS) module, part of SKA pulsar search. In FDAS, the frequency-domain input signals have to be processed by 85 421-tap FIR filters within a short time limit and for thousands of input arrays. Because of the large scale of input length and FIR filter size, even high-end FPGA devices cannot parallelize the task completely. We start by investigating both time-domain FIR filter (TDFIR) and frequency-domain FIR filter (FDFIR) to tackle the FDAS task. We applied the overlap-add algorithm (OLA) to split the coefficient array of TDFIR and the overlap-save algorithm (OLS) to split the input signals of FDFIR. To achieve fast prototyping design, we applied OpenCL, which is a high-level FPGA development technique, to develop high-end FPGAs. The performance and power consumption are evaluated and compared with GPU results, which is achieved by porting FPGA-based OpenCL kernels. The experimental evaluation shows that the FD solution is very competitive in terms of performance, with a clear energy consumption advantage over the GPU solution.