High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters

In High Efficiency Video Coding (HEVC) and H.264/AVC video coding standards, Interpolation filtering used for sub-pixel interpolation is one of the most computational intensive parts of the standards. Video processing systems are becoming more complex thus decreasing the productivity of the hardware designers and the software programmers, producing design productivity gap. To fill this productivity gap, hardware and software fields are bridged through High Level Synthesis (HLS), thus improving the productivity of the hardware designers. In this paper, we present a HLS based FPGA Implementation of sub-pixel Luma Interpolation of H.264/AVC. Xilinx Vivado HLS tools are used for the FPGA implementation of interpolation filtering on Xilinx xc7z020clg481-1 device. Our design can achieve the frame processing speed of 41 QFHD, i.e. 3840×2160@41fps. The development time is significantly decreased by the HLS tools.