Evaluation of fault attack detection on SRAM-based FPGAs

In this paper we present an extended fault injection approach to configuration memory of SRAM-based FPGAs consisting of inter frame many bits upsets to be used as an evaluation tool for attack detection capability and countermeasure effectiveness in security sensitive design modules. The work presented in this paper is twofold. First, we present the concept of a fault detection mechanism for SRAM-based FPGAs based on redundancy of functional modules to be placed evenly spaced over the FPGA floorplan and composing a fault detection mesh. On the following, we present the results of fault injection at the configuration memory of a SRAM-based FPGA used to evaluate the detection capability of different configurations of such detection module. To this, fault injection is done flipping many bits in sequence, locally, mimicking a laser attack. To demonstrate this concept, it was implemented in a Xilinx 7 Series device. The detection module used in the experiments was built around a substitution box (S-box) that is part of the Rijndael symmetric cryptography and the Advanced Encryption Standard (AES).