An Energy-Efficient Tensile-Strained Ge/InGaAs TFET 7T SRAM Cell Architecture for Ultralow-Voltage Applications

In this paper, we benchmark the read/write performance and standby power of several static random access memory (SRAM) cell architectures utilizing 45-nm Si CMOS MOSFET and/or tensile-strained Ge/InGaAs tunnel FET (TFET) devices under low-voltage operation (0.2 V ≤ |V
_DD
| ≤ 0.6 V). We then introduce a novel tensile-strained Ge/InGaAs TFET-based SRAM circuit using several access schemes and investigate the impact of cell access design on static and dynamic performance. SRAM cells utilizing outward access transistors exhibit wide read and write static noise margins, but suffer from increased read delay times. A 7T SRAM cell architecture is proposed in order to resolve the degraded read delay time. Cell standby energy was found to exhibit a strong dependence on operational voltage and Ge strain state. Variation of the Ge strain state from 1.5% to 3% resulted in an up to 98% reduction in cell standby energy (|V
_DD
| = 0.6 V) as compared with similar CMOS-based SRAM cells. These results demonstrate the superior performance of the proposed 7T TFET SRAM design for operation in the low- and ultralow-voltage regime.