Router architecture for the interconnection network: A review

High performance computing are useful in performing colossal amount of computation. Interconnect network is crucial when such a tremendous calculation is happening. In order to perform high speed computation, nodes in the system must be connected with a high speed interconnection network. HPC systems have computation and communication parts and performance is limited by communication network rather than computation network. Topology, routing, and flow control are design parameters for interconnect network. Routing algorithm helps the packet to move from source to destination. Router is the key element in implementing adaptive routing algorithm on hardware as it forwards packet from source node to destination through multiple hops. Scheduler and routing controller are responsible for actually forwarding packets based on routing algorithm. The important parameter considered while designing router is a switching technique. There are number of router architecture proposed earlier with switching techniques such as VCT and wormhole. This paper compares previous routers and describes the design of the router used for implementation of the adaptive algorithm on FPGA for 3D Torus. This router uses credit based flow control and Virtual cut through switching technique.