Containing guardbands

Reliability concerns may overtake conventional design constraints such as cost and performance because transistors in deep nano-CMOS era are increasingly susceptible to degradation effects. This made reliability become unsustainably expensive due to need for wider and wider guardbands (i.e. safety margins). It is in fact the time to reverse this trend: instead of widening guardbands, it is inevitable to contain them. In this work, we summarize three novel means to achieve this goal. Since the causes are of physical origin, it cannot be excluded that degradation effects influence (i.e. amplify or cancel) each other. Hence, we first investigate the interdependencies of degradation effects demonstrating that they should jointly and not separately be modeled towards designing smaller, yet sufficient guardbands. Then, we show how aging-aware logic synthesis based on our so-called degradation-aware cell libraries, enables designers to employ mature optimization algorithms available in the commercial synthesis tools to obtain more resilient circuits in which guardbands are inherently contained. Finally, instantaneous transistors aging is a recent discovery that bears a large potential for reliability optimization since it is hardly explored until now. Though aging in general has been extensively studied in last decade, investigating the impact of instantaneous aging on circuits' reliability is still in its infancy. In fact, this is a paradigm shift in aging from sole long-term reliability degradation, as in the traditional view, to short-term reliability degradation. We demonstrate how employing our physics-based aging models results in considerably smaller guardbands due to the high certainty compared to empirical aging models.