TDDB-emerald: A methodology for estimating memory reliability degradation resulting from time-dependent dielectric breakdown

One of the major wearout mechanisms in modern microprocessors is time-dependent dielectric breakdown. Beyond the 28 nm technology node, time-dependent dielectric breakdown from not only the frontend-of-line and backend-of-line, but also the middle-of-line, yields a significant number of failures in VLSI circuits. In this paper, we investigate the impact of time-dependent dielectric breakdown in all phases of fabrication processes (i.e., frontend/middle/backend-of-line) on static random access memory in modern microprocessors. With the analysis of potential resistive short defect locations in a memory cell, we propose a methodology for accurately estimating memory reliability degraded by time-dependent dielectric breakdown. Using activity profiles and device-level wearout models, we also propose a method for statistically estimating the lifetime of a memory cell. Using the simulation methodology, we investigate the lifetime degradation of a memory system while taking all three time-dependent dielectric breakdown mechanisms into account.