RapidLink: A network-on-chip architecture with double-data-rate links

Various state-of-the-art Network-on-Chip (NoC) architectures, employing either low-or high-radix topologies, have exploited the speed provided by on-chip wires - after appropriate wire engineering - to transfer flits over longer distances in a single clock cycle. In this work, motivated by the same principle of fast link traversal, we propose the RapidLink NoC architecture, which exploits said speed to rapidly transfer flits between adjacent routers (connected with links of reasonable short-to-medium length, up to a few millimeters) in half a clock cycle, thereby enabling Double-Data-Rate (DDR) link traversal. RapidLink can markedly increase network performance, without increasing the area/power cost of the NoC. Extensive cycle-accurate network simulations and hardware implementation results demonstrate the efficiency of RapidLink and its potential as a scalable NoC architecture.