Temperature study of defect generation, under channel hot carrier stress for 35-nm gate length MOSFETs using the Defect-Centric perspective

In this work, we present an analysis to separate the interface states generation from the oxide traps generation during channel hot carrier degradation, for several temperatures. At first, we use the defect-centric framework in order to extract the total number of traps generated during the channel hot carrier stress. Then, we study the exponent of the power law of the number of traps in function of the stress time. Under this analysis, we can extract the ratio of generated interface states with respect to the oxide traps caused by the CHC degradation. Finpower law of the number of traps in function of the stress time. Under this analysis, we can extract the ratio of generated interface states with respect to the oxide traps caused by the CHC degradation. Finally, we found that interface states are twice larger than oxide traps, which canally, we found that interface states are twice larger than oxide traps, which can be explained by extracting the activation energy for both generation processes.