Power efficient modulo convolution

In signal processing systems, the fundamental computation is nothing but convolution which is found in many application areas. The main building blocks are the multipliers to calculate convolution. But multipliers are the main power consuming elements. In recent years power is an important constraint. Now days, linear convolution has been implemented using distinct types of multipliers to decrease power dissipation. In this paper, modulo linear convolution have been proposed using modulo multipliers based on Radix-8 booth encoding algorithm for bits n=8, 16, 32 and 64. The modulo design is coded in Verilog HDL, Xilinx 14.7 has been used to perform Simulation and Synthesis. The proposed technique efficiently speeds up the computation which in turn decreases power dissipation, hardware resources and area significantly.