Design and implementation of livetap for deterministic ethernet bus using FPGA

Ethernet is the most commonly used LAN technology and popularly used since few decades due to its low cost and high speed. The use of Ethernet based communication networks in aerospace application is increasing with the present technology. Data traffic between the end systems are critical in avionics systems. It is important to monitor network traffic to understand the flow of data between the systems without disturbing the communication. The conventional software based network monitoring systems lags the feature for capturing live data between Ethernet nodes. This paper describes the design of FPGA based live tap to monitor the traffic between the two end systems. This technique shall be used where the Ethernet bus traffic monitor is prominent. The timing analysis of Ethernet packets is critical in the avionics application to characterize frame transmission and reception. The paper describes the technique for monitoring the packets in both the directions at 10/100Mbps along with the communication to the host for visualization. The IP core for the proposed approach has been developed using the Xilinx tool and is implemented on Xilinx SP605 evaluation board, which is connected to a monitoring systems for visualization at 1Gbps.