Instruction rearrangement and path limitation for ALU cascading

Nowadays, many-core processors utilize 2-way in-order execution cores due to good area/energy efficiency. Those cores are diverted from high-performance embedded processor so that it is convenient from the core development cost viewpoint. We can easily create 3-way in-order execution unit as a simple expansion of 2-way in-order execution. However, it makes few IPC improvement due to data dependency of instructions. Applying ALU cascading to 3-way in-order execution is a effective solution to alleviate this problem. In this study, we proposed a mechanism which limits cascading data path in ALU stage. Due lo lightweight data path, we improved both power consumption and delay in ALU stage of the processor. This study showed that the proposed mechanism can reduce the circuit area by 5.5% and the power consumption by 9.2% on average.