Reliability assessment of FPGAs

This paper presents a probabilistic methodology applied to FPGAs (Field Programmable Gate Arrays) logical structures known as basic building blocks, namely: CLBs (Complex Logic Blocks), usually consisting of LUTs (Look-up Tables) and biestables (flip-flops), PSWs (Programmable Switch Matrixes), IOBs (Input-Output Blocks), SMRAs (Static Random Access Memories) and CBs (Connection blocks). The scope of this paper is to investigate and analyze the possibility of using this methodology in assessing the reliability of emerging structures that use FPGAs in electronic developments based on the evaluation models of logic circuits proposed by the author and extending these concepts at the system level. For this purpose the RELEX-Reliability Studio PTC software is used to model the system, moving the research and analysis to the plane of Fault Tree Analysis (FTA).