Spurious source/drain underlap of large junction area NFET's

When a 0.35-/spl mu/m CMOS technology was introduced into manufacturing, a small fraction of the tested devices exhibited symptoms of source/drain underlap, despite the fact that all other monitors were well within the design control limits. Additional measurements showed variable overlap on various monitor structures on the same chip. The specific formulation of an HF wet clean was shown to be responsible for the underlapped devices, and the problem was eliminated by altering this process step. High-volume manufacturing data are presented to show the problem and the solution.