A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells

This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 /spl mu/m CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip.