Low power multiplier using algorithmic noise tolerant architecture

In this paper, Fixed-width Reduced Precision Replica Redundancy Block (RPR) design is adopted in Algorithmic Noise Tolerant (ANT) architecture. The main objective of this design is to achieve High Precision, Low power and high speed multiplier. By using Fixed-width RPR computation error can be identified and corrected. The ANT architecture was implemented using Xilinx and ModelSim tool. Performance metrics of power is compared with existing Full-width RPR designs. Average Power consumption of the proposed design is found to be 74.42μW at 100Hz. Proposed design achieves less power and area efficiency than the Full-width RPR.