Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter

State-of-art Multiprocessor Systems-on-Chip (MPSoC) struggle to respect the increasing requirements of high performance interconnects for high throughput communications. Optical integrated Networks (OIN) represent currently one of the most promising paradigms for the design of such next generation MPSoC. They provide increased bandwidth and better reaction to electromagnetic noise while decreasing latency and power consumption. In this paper we propose a new cluster-based architecture, the Hybrid Torus MPSoC (HTM). We propose also a low-latency arbiter allowing to exploit the full potential of the HTM architecture. Our experiments, based on FPGA prototyping and simulation, show the efficiency of the proposed architecture.