The impact of rate mismatch in ATM switch design

This paper evaluates the buffer requirements resulting from rate mismatch in a 32/spl times/32 ATM switch with sixty OC-3 (155 Mbps) and four T-1 (1.5 Mbps) ports. Rate mismatch is expected to be a common occurrence in ATM wide area networks, particularly at the network seams. Without proper dimensioning, the switch buffers can rapidly overflow as a result of high-speed input traffic destined to a low-speed port. We specifically consider the Cisco Systems LightStream 1010 ATM switch architecture in our analysis, and compare the design options of a larger common shared buffer with that of adding buffers to each T-1 output port. We consider traffic from individual high-speed servers, LAN workstations, and aggregated Ethernet traffic.