Performance enhancement of multistage interconnection networks with unit step buffering

Multistage interconnection networks (MINs) have been widely used for parallel computer systems, and also recognized as an efficient switching fabric for digital communication. In this paper, we propose a new switching mechanism for MINs called unit step buffering (USB) which significantly improves the network performance. Here each cell is allowed to move only one buffer entry position using short network cycle. The proposed USB scheme is compared to the traditional scheme by analytical modeling and computer simulation. They reveal that throughput and delay are improved about 60%-80% for practical size MINs with reasonable traffic in the asynchronous transfer mode (ATM) switching environment. Improvement on parallel computer systems with larger size packets is more significant at about 100%. More importantly, the scheme does not require any additional hardware or operational overhead.