Electrical design and design automation for packaging

One important challenge in the electrical design of electronic packaging is encountered in the many systems requiring processors operating at clock frequencies in the hundreds of Megahertz. The competition to provide higher performance computers results in an increasing number of processors in a system and these processors are running at faster clock frequencies. The package needs to support wider buses at higher frequencies to connect the processors with each other and with cache and main memory data storage. Since the interconnects must run without interruption, the timing and noise characteristics of these paths must be characterized and managed. The short design cycle is supported by including the management of the timing and noise characteristics as an integral part of the high-level system design at the beginning of the project and then verifying that the same constraints are met for the formal design review before the finished designs are released into manufacturing. The principles we follow to design the packaging for multi-processor systems are presented. A methodology for design will be described which defines budgets and equations to efficiently calculate the timing and noise on the interconnects. This provides a means to include the electrical considerations in the optimal cost-performance choice of technology. The budgets and equations are then integrated into the design tools and provide guidance in the design of the power and signal distribution and the means for thorough post-design verification of the electrical performance of the package in the system.