An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

In this paper a new algorithmic Analog-to-Digital Converter (ADC) is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in a digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2 um CMOS process show that an 8-b ADC can support a sampling rate of 50 MHz.