High speed IIR filter for XILINX FPGA

This paper makes a connection between digital signal representation, all potential two's complement multiplier for FPGA and one of the most original and powerful methods for multiplication: the Booth algorithm. The paper identifies the applications where constant coefficient multipliers cannot be used and states the advantages and drawbacks of all other techniques. At this point, the description of our anti-jamming IIR notch filter in XILINX FPGA becomes easier. This application note describes the functionality and integration of a real time IIR filter using 2 large multipliers at very high sampling rate in XC4020EPG223-2 device (up to 40 M samples/s). It also reveals the solution to an interesting design problem which emerges, and some additional enhancements since other papers, introducing a hybrid technique. Booth algorithm is shown to improve the CLB density and speed of FPGA circuit without any pipeline needed in IIR filtering.