RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs

Lowering the supply voltage of StaticRandom-Access Memories (SRAM) is key to reduce anintegrated circuit power consumption, however since thisbadly affects the circuit performances, it might lead tovarious failure modes of the memory circuit. While itis known that assist techniques can help in recoveringfunctionality, it is hard to find a detailed model of thosetechniques. In this work, static write- and read-assisttechniques are used to lower the minimum operatingvoltage VMIN of a high-density 6T SRAM circuitmanufactured in 40nm technology. A newly-developedspice-based method allows modeling at high computingefficiency the effects of static negative bit-line write-assistand the effects of static word-line under-drive read-assiston memory yield. Silicon results collected over a largetemperature range on a die population show that 100mVstatic negative bit-line is enough to lower the memorysupply voltage to Vddnom - 250mV safely. Despite itssimplicity, the model allows to reproduce the salientfeatures of silicon data.