Numerical calculation of gate-line delay in very large active matrix liquid crystal display with via holes

The size of active matrix liquid crystal displays (AMLCD's) is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. In this paper, the maximum gate-line delay for the new structure is analyzed with network theory. We found that the delay is influenced by the pixel time constant, the resistance ratio of top line to back line, the number of via holes, the number of pixels, and the resistance ratio of driver source to top line. Explicit equations are derived for these relationships. Numerical calculations are carried out to discuss interesting practical cases. Our results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten. The resistance ratio of driver to top line has an effect on the delay, and a linear equation is derived to describe this influence. The computed results agree with that from the SPICE simulation with high accuracy. Approximations of explicit equations are presented which can be very useful in the research and development of new structure.