System Applications Of A New 32-Bit Floating-point DSP Processor

Embodiment of DSP tasks requires an optimal blend of reg- ularly structured array processing and scalar oriented decisions making. The ZR34325 represents the first full IEEE floating- point integrated array processor on silicon, supplemented with the pertinent scalar and control flow capabilities. In order to meet the stringent processing requirements, found today in modern signal and image processing applications, the ZR34325 directly executes embedded DSP and array processing primitives on multidiniensional arrays. Furthermore, an integrated development environment which includes system software simulator, vectorized and parametric DSP, arithmetic and matrix library, C based assembler/linker and hardware development tools, facilitates top-down complete application development . To achieve performance bounds higher than plausible by a single device (45 MFLOPs peak), one must resort to a Multi- Processor Multi-Tasking (MPMT) schemes. The ZR34325 en- ables very efficient MPMT schemes for tasks where: (i) Execution- time is data independent (e.g. FFT); or (ii) Execution-time is data dependent (e.g. SVD algorithm).