A high speed shuffle bus for VLSI arrays

Due to the concerns of two dimensional layout and structural modularity, interprocess or data transfers for VLSI arrays, such as systolic/wavefront processors, are normally achieved by way of neighborhood communication. Although interconnection networks are designed to enhance global communication for non-systolic types of processing, it is not feasible to incorporate the processors and global interconnections on the same chip to obtain cellular structures. In this paper we propose a high speed shuffle bus as a means to fulfill various kinds of communication schemes for a processor array. Because of the simple and modular nature of the shuffle bus, the processor array can be modularized and equipped with global and near-neighbor communication capability.