Clustering and Mapping Algorithm for Application Distribution on a Scalable FPGA Cluster

The high flexibility of FPGAs predestines them for emulation and prototyping of ASICs. Despite the progress in VLSI technology, high performance FPGAs can be very cost intensive. To reduce these costs, we propose a scalable cluster of low cost mainstream FPGA boards. This paper presents a new approach for the distribution of application tasks into a cluster of FPGAs. The algorithm is split up into two main steps. Different solutions are computed for both steps in parallel, starting from different initial states. The first step does clustering and mapping at the same time, by unfolding the tasks in a two dimensional Euclidian vector space, limited to the boundaries of the FPGA cluster. Load balancing is done, by forcing nodes towards each other, dependent on the edge amount, and by forcing them apart from each other, depending on the FPGAs capacity utilization. The second step optimizes the logic utilization of each FPGA and minimizes the maximum dilation (number of edges of a path to which an edge is mapped), by using different heuristics. A gradient descent algorithm (improved variant of the local search) is combined with simulated annealing and extended by a taboo search algorithm, to avoid cycles and exit local minima.