A 24 mW, 80 dB SNR, 50 MHz multi-bit continuous time ΣΔ ADC in 28 nm FD-SOI

This paper presents a continuous time sigma delta ADC for 50 MHz bandwidth with 80 dB resolution, which overcomes the shortcomings of known architectures. It incorporates a 5 bit flash ADC as a quantizer with a current steering feedback DAC employing dynamic element matching. The main feedback path and the fast feedback path around the quantizer have shifted delays to compensate for the excess loop delay. The architecture uses 28 nm FD-SOI technology with flipped well transistors having forward body bias. Circuit simulations predict a power consumption of 24 mW at a 1.0 V supply voltage, and state-of-the-art Schreier FOM of 173 dB.