Power noise in 14, 10, and 7 nm FinFET CMOS technologies

A methodology is described to determine the distribution of current within a power network for use in CMOS standard cell integrated circuits based on exploratory information about the power network. Models are presented to extrapolate the noise within power networks in 14, 10, and 7 nm CMOS technologies. Stripes, interconnect between local power rails, are evaluated as a means to reduce power noise, resulting in a 56.5% reduction in noise for the 7 nm CMOS technology node.