A topology for network-on-chip

Network on chip is an advanced version of System on chip which gives both scalabilities and flexible communication inside the chip. In this paper we proposed a new topology by keeping in mind the factors like minimum chip area, high throughput and minimum latency with path diversity. We compared our proposed topology with some existing topologies like fat tree and Multipath Topology in terms of latency, throughput, hop count, the hardware used and the number of events to be carried out the simulation. The proposed topology provides us with minimum latency, less hardware used, high throughput better than the existing topologies that we compared. We used an adaptive routing algorithm which is a deadlock and live lock free algorithm, provides path diversity along with a proper load balance and maximum channel utilization in our proposed topology. The required simulation is done using with an open source simulator named OMNET++.