Current-mode capacitance multiplier with reduced parasitic elements

This paper presents a method of implementing a large virtual capacitor using an area-efficient capacitance multiplier circuit. The multiplier solves the major issue of large area consumption in integrated circuits needing high capacitance values. The proposed architecture improves other important parameters, such as the quality factor and the operating signal range. An analytical equivalent model is derived. The circuit is completely characterized in terms of model parameters and voltage and frequency operating ranges. Simulations are run to confirm feasibility and performance. An experimental version is implemented using discrete devices. A comparison between the theoretical, simulated, and experimental results is made.