An approach of MPRA technique over ARM cache architecture

This paper aim is to present the development and testing of a nMPRA (Multi Pipeline Register Architecture for N tasks) architecture, described in [1], on an Amber (opencore) system, based on an ARM with cache architecture. The internal, status and pipeline registers, as well as cache memory were multiplied. Two similar applications were tested: the first one (made of four do-while loops) was tested on an unmodified Amber system. In the second one, a similar algorithm was tested on 4-MPRA architecture, every do-while thread rans on one of four register set separately. The threads ran simultaneously. As a result, we obtained an approximately 30% increased of the processing speed for the same job (divided in four separated threads).