Hybrid soft error mitigation techniques for COTS processor-based systems

In this paper we combine a set of software-based fault tolerance techniques with a hardware module that monitors the trace port, and explore from an experimental point of view the fault coverage against soft errors in COTS processors that can be achieved. The costs in terms of performance and memory are also evaluated. Fault injection results show fault coverage is superior to the state-of-the-art techniques with lower performance and memory overheads.