A control path aware metric for grading functional test vectors

Functional, at-speed test vectors play a critical role in targeting circuit defects not easily detected by traditional scan vectors. Fault simulating these vectors is generally computationally expensive since these tests are often applied at the system level without individual testing of modules within the hierarchy. As a result, fault grading techniques have become necessary to judge the quality of these test vectors. In this work, we propose a control path aware, rule-based statement coverage metric at the Register Transfer Level (RTL) to capture faulty behavior of statements along distinct operation paths within the circuit description. Experiments show that our metric has a strong correlation with gate level defect models across a variety of benchmarks, including the microprocessor or 1200 with a power management unit. Additionally, the metric shows high levels of scalability, providing up to two orders of magnitude reduction in execution time compared to fault simulation and up to an order of magnitude improvement over logic simulation based fault grading techniques.