On the relation between bit delay for slot reuse and the number of address bits in the dual-bus configuration

In slotted, dual-bus systems, M stations are connected to two unidirectional buses in a linear order and transmissions use slots passing through the stations. If a slot is used by a station i to transmit to a station j, j>i, then the slot can be reused by a station k, k/spl ges/j. We show that the necessary and sufficient length of addresses for full slot reuse is M-2 bits for w=0 and [(M-1)/2/sup w-1/]+w-2 bits for w/spl ges/1 and M>1+2/sup w/, where w is the bit delay at every station.