Dependencies data flow graph based approach for speeding-up application

This paper bring a description of `HSCoT', an efficient high level synthesis tool generating register transfer level (RTL) specifications for applications written entirely in C language and an associate reliable approach for speeding applications execution. It's based on dependency data flow graph construction and aims to explore maximally the inherent intrinsic parallelism of application. Application written in algorithmic C specifications will be parsed, transformed on intermediate representation (IR) and dependency data flow graph and restructured once again in novel statements sequences that can be executed in shortest time on parallel architectures as FPGAs. The tool permits the efficient mappings at the fine and coarse granularity levels, and in this earliest release, it gives developers the opportunity to generate the fastest IP cores. The reliability of the approach is proved on carrying the outcomes of accelerations acquired for some IP cores synthesized by the associate tool compared to those achieved by some market and open source cores.