Design of a configurable fixed-point FFT processor

In this paper, we focus on the widely-used radix-2
²
Decimation-In-Frequency (DIF) Fast Fourier Transform (FFT) algorithm. A variable-length, controllable-precision FFT processor is proposed. The processor can perform 16, 64, 256 and 1024 point FFT/IFFT and provide flexible wordlength scaling modes for different FFT stages. Thus, the processor is suitable for different precision and FFT length requirements in various applications. Aiming at high throughput performance, single-path delay feedback (SDF) pipeline architecture is adopted. The design is testified on Xilinx Virtex6 xc6vcx240t FPGA. Accordingly, we make a clear comparison between the proposed design and Xilinx FFT v7.1. Our design achieves better signal-to-quantizationnoise ratio (SQNR) property and shorter pipeline latency. Meanwhile, the occupied resource is approximately the same. Moreover, SQNR performance of different FFT length and wordlength scaling modes is analysed.