Digital multiphase clock/pattern generator

In telecommunications systems, the commonly used method to generate clocks is based on phase-locked loop or delay-locked loop related frequency synthesis. In this paper, we address a method of digital multiphase clock/pattern generation (MPCG) to generate a system clock or pulse pattern vector when a multiphase clock is available. The advantages of the multiphase clock method are: (a) the design method is digital; (b) the working frequency range is very wide; and (c) the sensitivity to noise is less than analog methods. Different approaches to implement the basic blocks in MPCG are described. A design example implemented in BiCMOS uses eight clock phases at 622 MHz obtained by dividing a 5-GHz clock to generate a clock at 622 MHz/spl times/32/53=376 MHz. By such a method, we can generate a pulse pattern vector as well. The maximum time resolution is equal to half of the phase difference. A low power solution is achieved without loss of circuit speed.