Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence Support

Efficient and low latency solution to cache coherence problem in shared memory multicore systems on Network-on-Chip (NoC) is a crucial issue for improving system performance and scalability. The existing works utilize planar metal/dielectric interconnects to solve this problem. However, as the number of cores on chip increase, such solutions face high latency due to increase in long-range multi-hop communication between distant cores. In this paper, we propose a novel multicore hierarchical cluster based architecture that utilizes a hybrid NoC having both wired and wireless interconnects. The wireless interconnects on chip replaces the long-range multi-hop communication path to single-hop low latency connections. We also propose a utilization based clustering of cores. Finally, we present a novel cache coherence algorithm for the designed architecture. To the best of our knowledge, our work is the first to utilize wireless interconnects to address the cache coherence problem in NoC based multicore system. We evaluate our system through analytical as well as system level simulations on GEM5 running SPLASH2 and PARSEC benchmarks. Through our evaluations, we find that our proposed architecture achieves an average of 94.4% reduction in overall memory overhead, 30% reduction in average L2 access latency and 32.1% reduction in L2 miss rate compared to conventional non-clustered directory architecture. Our solution also exhibits a notable decrease in overall execution time, memory requests and miss latency for all benchmarks.