Heterogeneous Integration for Performance and Scaling

Moore's law has so far relied on the aggressive scaling of CMOS silicon minimum features of over 1000× for over four decades, and recently, on the adoption of innovative features, such as Cu interconnects, low-k dielectrics for interconnects, strained channels, and high-k materials for gate dielectrics, resulting in a better power performance, cost per function, and density every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. In this paper, we show that with the apparent slowing down of semiconductor scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging is undergoing a transformation that focuses on overall system performance and cost rather than on individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. This transformation is already under way with 3-D stacking of dies and will evolve to make heterogeneous integration the backbone of sustaining Moore's law in the years ahead.