27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS

A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its output power is mostly delivered by a Nyquist MSB path, resulting in a reduced number of current-steering cells and relaxed amplitude-matching requirement via digital pre-distortion in the LSB path. To further extend the DAC bandwidth, this architecture incurs high cost, such as higher oversampling ratio in the LSB path and an increasing number of MSB bits. Both cases can increase the complexity of the analog circuit. Moreover, when the DAC output frequency is higher, timing error effects (including delay and duty-cycle errors) become more important than that of the amplitude error. In this work, we propose: a) an in-band noise-cancellation scheme that extends the overall bandwidth with less overhead, and b) a pulsed timing-error pre-distortion scheme to achieve high linearity at higher frequencies. A proof-of-concept 12b 2GS/s hybrid DAC is implemented in 65nm CMOS that achieves 96 to 74dBc SFDR from DC to 1GHz Nyquist band, which is higher than that of the state-of-the-art high-speed (>1GS/s) CMOS DACs reported in [2-4], compared at the same output frequencies. The proposed pulsed timing error pre-distortion scheme also improves the SFDR from 68 to 74dBc at 949MHz, which confirms its effectiveness when the signal frequency is high.