A novel circuit for clock synchronization using binary search scheme and phase interpolation

In this paper, a novel circuit for clock synchronization utilizing an interleaved delay line for coarse tuning and a phase interpolation component for fine tuning is proposed. The interleaved delay line improves the precision to nearly half of conventional SMD and roughly aligns the output clock in two cycles. The rest phase error is compensated by the fine tuning component with binary search scheme and phase interpolation in five clock cycles and the error is suppressed under 3.1 ps. The circuit is designed and implemented using SMIC 130 nm 1P8M process with a 1.2 V voltage supply. The active area of proposed circuit is 260µm×140µm, and the total power consumption is 1.82mW@500MHz. The allowed operation frequency ranges from 200 MHz to 860 MHz, and the duty cycle varies in [32%, 77%]. It is compatible with the clock distribution networks and clock tree synthesis workflow aided by EDA software.