FlexCore: A Reconfigurable Processor Supporting Flexible, Dynamic Morphing

In the realm of desktop and server class processors, the prevailing trend is to use out-of-order superscalar cores that exploit the hidden instruction-level parallelism in a program. In superscalar designs, the performance (as measured by the IPC, instructions committed per clock cycle) does not go up linearly with the dispatch width, say, n, due to dependencies in the program and higher branching penalties that are encountered with an increase in n. Furthermore, the area requirement of a superscalar processor grows more than linearly with n, leading to poor energy efficiency (IPC per Joule of expended energy) for higher values of n. This paper introduces FlexCore, a reconfigurable multicore datapath where the processing resources, dispatch width and operating modes (in-order, out-of-order, simultaneously multithreaded execution) are dynamically adapted based on the instantaneous needs of the executing application to avoid overcommitting any processing resource. In FlexCore, unutilized or underutilized processing components are shut down to save power and realize higher energy efficiency compared to a baseline out-of-order multicore chip with a fixed core configuration. FlexCore, regardless of the specific reconfiguration mode, always presents the same number of virtual processors to the Operating System and thus requires no OS modifications. A cycle-accurate simulation of FlexCore or many-threaded and multi-threaded applications show that significant improvements in energy efficiency are realized over the baseline design with little or no impact on performance.