Design and physical implementation of a data transfer interface used in network on chip

The implementation of an efficient network on chip (NOC) requires the design of efficient network interfaces (NI) which connects the intellectual's properties (IPs) to the routers. According to the NOC topologies, these NIs may be different. In this paper, we present at first the design of a novel architecture of a data transfer interface (DTI) which will be used in a new paradigm of network on chip, and then, we present the results of the verification and the physical implementation of this DTI. Because of the frequencies between the IPs and the network on chip are often different, the DTI is used for synchronizing data and avoiding the metastability risk. It is also used for storing the data in a FIFO in order to avoid losing them during the transfer. The DTI was designed with Verilog language, the verification was done by the Modelsim tool and finally the logical synthesis and the physical implementation were achieved by Cadence RTL Compiler and Encounter Digital Implementation respectively.