A high throughput pipelined hardware architecture for tag sorting in packet fair queuing schedulers

In a timestamp-base packet scheduler, which is an important part of Quality of Service (QoS) enabled network systems, Tag Sorting is the most critical step. This paper presents a high throughput pipelined architecture for Tag Sorting targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at a maximum clock frequency of 216 MHz and process one tag every 2 clock cycles, thus provides 108 million tags per second throughput and can support 100 Gbps line speeds.