Advanced Fabrication Processes for Superconducting Very Large-Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where “ee” denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoN
_x
layer (T
_c
~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (T
_c
<; 2 K) MoN
_x
layer with lower nitrogen content is used for 6-Ω/sq planar resistors for shunting and biasing of Josephson junctions (JJs). Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlO
_x
-Al/Nb JJs with critical current density J
_c
of 100 μA/μm
²
and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO
₂
interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, I
_c
and J
_c
targeting, effect of hydrogen dissolved in Nb, MoN
_x
properties for the resistor layer and for high-kinetic-inductance layer, and technology of milliohm-range resistors.